FIG. 1 shows the typical input receiver wordline driver circuit of the prior art generally shown by 10. This circuit is designed to interface with wordlines such as wordline 34 and wordline 36. These wordlines may also be driven by high voltage drivers located elsewhere in the semiconductor chip to approximately twelve volts during the programming of the memory array. Therefore, the input receiver and wordline driver circuit 10 is designed so as to be able to interface with wordlines 34 and 36 and to accommodate possible high voltages on these wordlines. For example, circuit 10 must be able to isolate the ground voltage or the supply voltage from wordlines 34 and 36 when these wordlines are driven to a high voltage.
Inverter 12, which is typically designed to respond to TTL input levels, drives a buffer 50. Buffer 50 provides a sufficiently strong drive and sharp rise and fall edges to drive wordline 34. Thus, the combination of inverter 12 and buffer 50 is dedicated to drive wordline 34. Since, as stated above, wordline 34 may be driven to a high voltage of approximately twelve volts, buffer 50 is also used to isolate the possible high voltage on wordline 34 from the ground voltage.
Transistors 26 and 32 are used to perform this isolation of any high voltage on wordline 34 from the supply voltage and the ground voltage respectively. Transistor 26 is used to isolate the possible high voltage on wordline 34 from the supply voltage. The gate of transistor 26 is driven by signal HDWL as shown in FIG. 1. This signal switches to a high state, and thus turns off p-channel transistor 26, whenever wordline 34 is driven by a high voltage driver. Thus, when wordline 34 is being driven by a high voltage driver the electrical path between that wordline and the supply voltage is cut off by the action of signal HDWL and transistor 26 as described above. Similarly, transistor 32 is employed to isolate the possible high voltage on wordline 34 from the ground voltage. The gate of transistor 32 is driven by signal EWLS as shown in FIG. 1. This signal switches to a low state, and thus turns off n-channel transistor 32, whenever wordline 34 is driven by a high voltage driver. Thus, when wordline 34 is being driven by a high voltage driver the electrical path between that wordline and the ground voltage is cut off by the action of signal EWLS and transistor 32 as explained above.
Transistors 28 and 30 of buffer 50 are responsible for driving wordline 34. Transistors 28 and 30 respond to the variations on their common gate 15. The common gate 15 is driven by inverter 12 and shown in FIG. 1. Thus, the combination of inverter 12 and buffer 50 is a non-inverting combination which drives wordline 34 in response to variations in the input VIN of inverter 12.
In a similar manner, inverters 14 and 16 along with buffer 40 drive wordline 36. Like buffer 50, buffer 40 performs the function of providing a strong drive for wordline 36 as well as performing the function of isolating any high voltage on wordline 36 from the supply voltage or ground voltage lines. However, unlike the combination of inverter 12 and buffer 50, the combination of inverters 14, 16 and buffer 40 is an inverting combination. Thus, wordline 16 and buffer 40 is an inverting combination. Thus, wordline 36 represents an inverted version of wordline 34. Because of the additional inverter use to create the inverted wordline 36, wordline 36 makes its transitions with an added delay as compared to the transitions of wordline 34. In particular, the low to high transitions of wordline 36 are delayed, by one inverter delay time, from the low to high transitions of wordline 34.
It is therefore an object of the present invention to create an inverted version of a wordline, without rendering the low to high transition of the inverted wordline slower than the low to high transition of the non-inverted wordline.